A memory device package typically includes a semiconductor memory die encased in a plastic or ceramic casing, and package contacts that enable the device package to be electrically connected to a printed circuit board (PCB). Memory device packages can have package contacts that come in many different forms. FIG. 1A shows one device package 100a having package contacts in the form of metal leads 102 that are connected to an underlying PCB 103. The metal leads 102 are arranged in a lead frame 104 and extend through a package casing 105 where they connect to a memory die 106 within the package casing 105. Wirebonds 108 electrically connect individual leads 102 to individual die bond pads 107 on an upper side of the memory die 106, thereby electrically connecting the memory die 106 to the PCB 103. The device package 100a shown in FIG. 1A is commonly referred to as a small outline integrated circuit (SOIC) package.
FIG. 1B shows a different memory device package 100b having package contacts in the form of contact pads 112 bonded to the PCB 103 generally beneath the device package 100b via metal solder bumps 115. The contact pads 112 are formed on a support substrate 114 that carries the memory die 106. The support substrate 114 includes multiple levels of conductive traces (not shown) that connect the contact pads 112 to the corresponding wirebonds 108 and die bond pads 109 on the memory die 106. The device package 100b shown in FIG. 1B is commonly referred to as a ball grid array (BGA) package.
One difference between the BGA package 100b of FIG. 1B and the SOIC package 100a of FIG. 1A is that the BGA package uses the support substrate 114 in lieu of the metal leads 102 to route electrical connections. An advantage that this provides is a more compact footprint than the SOIC package 100a due to the package contact pads 112 being within planform of the memory die 106. Additionally, it is easier to route electrical connections using the substrate traces of the BGA package 100b rather than the metal leads 102, which can only be placed along the perimeter of the die 106. A disadvantage of the BGA configuration, however, is that the support substrate 114 is more expensive to manufacture than the lead frame 104, and thus increases the relative cost of the BGA package 100b. To keep manufacturing costs low, some device manufactures choose to use an SOIC package, while other manufactures choose a BGA design for a reduced footprint and less complicated die bond pad layout. In either case, the memory die 106 of the BGA and SOIC packages can be substantially identical, except for the layout of the corresponding die bond pads 107 and 109.